1. Field of the Invention
The present invention relates in general to integrated circuits of the type called programmable logic devices, and more particularly to a macrocell associated with a programmable memory array provided with an EPROM transistor or an EEPROM transistor.
2. Description of the Prior Art
For implementing logic functions, there have broadly been used a type of integrated circuits known as erasable and programmable logic devices (EPLDs) or electrically erasable and electrically programmable logic devices (EEPLDs).
Such EPLD structures are at the beginning shown in U.S. Pat. Nos. 4,609,986 and 4,617,749. In logic devices as disclosed in the above patents, there is provided an AND array configured to form a plurality of "product terms" which are fed into an OR array, the outputs of which form sum-of-products expressions of the inputs to the AND array. The ORing of product terms is each either coupled to an output pin through an input/output (I/O) circuit in each of a plurality of macrocells, or fed back to the AND array, so that each macrocell is capable of performing various combinatorial logics or sequential logics. The macrocells shown in the above patents each receives the predetermined number of product terms from the AND array and ORs the received product terms. The ORing of product terms is each received to the input/output (I/O) circuit in each of the macrocells. The adjacent macrocells are independent of each other.
However, in such structures shown in the above patents, because the product terms fixed in number or ORed, the product terms are wasted in the case where a logic is embodied which requires product terms smaller in number than the product terms previously fixed in number, and another macrocell should be added for use in the case where a logic is embodied which requires product terms larger in number than the product terms previously fixed in number. As a result, an efficiency of the macrocell is degraded in use. Also in such structures, there is present one ORed path, i.e., one sum data path for product terms per macrocell, making it impossible to use a register in the macrocell when a system user tries to embody a combinatorial logic in the designated macrocell. More particularly, the register is limited in number to that identical to the macrocell, thereby causing a degradation in an efficiency of the register in use.
U.S. Pat. No. 4,878,200 shows a method of allowing product term sharing/allocation by adjacent macrocells for the efficient use of product term. In such structure in the above U.S. Pat. No. 4,878,200, two groups of four product terms each are coupled to each macrocell, wherein the ORing of each group of four product terms is each coupled to a multiplexor. One group is also coupled to a previously adjacent macrocell and the second group is coupled to a subsequently adjacent macrocell. As a result, the macrocell requiring larger product terms in number can share product terms with the adjacent macrocell, and the macrocell requiring smaller product terms in number can allocate product terms to the adjacent macrocell. However, also in such structures, there is present one ORed path, i.e., one sum data path for product terms per macrocell, causing the above-mentioned problem as shown in the above U.S. Pat. Nos. 4,609,986 and 4,617,479.
In result, there is a necessity for using the function of the macrocell efficiently, with the product term.